1 cat24wc01/02/04/08/16 1k/2k/4k/8k/16k-bit serial e 2 prom * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. pin configuration block diagram pin functions pin name function a0, a1, a2 device address inputs sda serial data/address scl serial clock wp write protect v cc +1.8v to +6.0v power supply v ss ground dip package (p) 24wcxx f03 soic package (j) 5020 fhd f01 features n 400 khz i 2 c bus compatible* n 1.8 to 6.0volt operation n low power cmos technology n write protect feature entire array protected when wp at v ih n page write buffer n self-timed write cycle with auto-clear n 1,000,000 program/erase cycles n 100 year data retention n 8-pin dip, 8-pin soic or 8 pin tssop n commercial, industrial and automotive temperature ranges description the cat24wc01/02/04/08/16 is a 1k/2k/4k/8k/16k- bit serial cmos e 2 prom internally organized as 128/ 256/512/1024/2048 words of 8 bits each. catalysts advanced cmos technology substantially reduces de- vice power requirements. the the cat24wc01/02/04/ 08/16 feature a 16-byte page write buffer. the device operates via the i 2 c bus serial interface, has a special write protection feature, and is available in 8-pin dip, 8- pin soic or 8-pin tssop. ? 1998 by catalyst semiconductor, inc. characteristics subject to change without notice 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 v ss 1 2 3 4 tssop package (u) (* available for 24wc01 and 24wc02 only) d out ack sense amps shift registers control logic word address buffers start/stop logic state counters slave address comparators e 2 prom v cc external load column decoders xdec data in storage high voltage/ timing control v ss wp scl a 0 a1 a2 sda a 2 a 0 a 1 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda a 0 v cc wp scl sda 1 2 3 4 8 7 6 5 a 1 a 2 v ss doc. no. 25051-00 3/98 s-1
cat24wc01/02/04/08/16 2 doc. no. 25051-00 3/98 s-1 absolute maximum ratings* temperature under bias ................. C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ........... C2.0v to +v cc + 2.0v v cc with respect to ground ............... C2.0v to +7.0v package power dissipation capability (ta = 25 c) .................................. 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. limits symbol parameter min. typ. max. units test conditions i cc power supply current 3 ma f scl = 100 khz i sb (5) standby current (v cc = 5.0v) 0 m av in = gnd or v cc i li input leakage current 10 m av in = gnd to v cc i lo output leakage current 10 m av out = gnd to v cc v il input low voltage C1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage (v cc = 3.0v) 0.4 v i ol = 3 ma v ol2 output low voltage (v cc = 1.8v) 0.5 v i ol = 1.5 ma note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. (5) standby current (i sb ) = 0 m a (<900na). capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test max. units conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a0, a1, a2, scl, wp) 6 pf v in = 0v
cat24wc01/02/04/08/16 3 doc. no. 25051-00 3/98 s-1 a.c. characteristics v cc = +1.8v to +6.0v, unless otherwise specified. read & write cycle limits symbol parameter 1.8v, 2.5v 4.5v-5.5v min. max. min. max. units f scl clock frequency 100 400 khz t i (1) noise suppression time 200 200 ns constant at scl, sda inputs t aa scl low to sda data out 3.5 1 m s and ack out t buf (1) time the bus must be free before 4.7 1.2 m s a new transmission can start t hd:sta start condition hold time 4 0.6 m s t low clock low period 4.7 1.2 m s t high clock high period 4 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 50 50 ns t r (1) sda and scl rise time 1 0.3 m s t f (1) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 m s t dh data out hold time 100 100 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. write cycle limits symbol parameter min. typ. max units t wr write cycle time 10 ms power-up timing (1)(2) symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms
cat24wc01/02/04/08/16 4 doc. no. 25051-00 3/98 s-1 functional description the cat24wc01/02/04/08/16 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. data transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat24wc01/ 02/04/08/16 operates as a slave device. both the mas- ter and slave devices can operate as either transmitter or receiver, but the master device controls which mode is activated. a maximum of 8 devices (24wc01 and 24wc02), 4 devices (24wc04), 2 devices (24wc08) and 1 device (24wc16) may be connected to the bus as determined by the device address inputs a0, a1, and a2. pin descriptions scl: serial clock the cat24wc01/02/04/08/16 serial clock input pin is used to clock all data transfers into or out of the device. this is an input pin. sda: serial data/address the cat24wc01/02/04/08/16 bidirectional serial data/ address pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. a0, a1, a2: device address inputs these inputs set device address when cascading mul- tiple devices. when these pins are left floating the default values are zeros (except for the 24wc01). a maximum of eight devices can be cascaded when figure 2. write cycle timing figure 1. bus timing figure 3. start/stop timing 5020 fhd f05 5020 fhd f04 5020 fhd f03 t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh t wr stop condition start condition address ack 8th bit byte n scl sda start bit sda stop bit scl
cat24wc01/02/04/08/16 5 doc. no. 25051-00 3/98 s-1 using either 24wc01 or 24wc02 device. all three address pins are used for these densities. if only one 24wc02 is addressed on the bus, all three address pins (a0, a1and a2) can be left floating or connected to v ss . if only one 24wc01 is addressed on the bus, all three address pins (a0, a1and a2) must be connected to v ss . a total of four devices can be addressed on a single bus when using 24wc04 device. only a1 and a2 address pins are used with this device. the a0 address pin is a no connect pin and can be tied to v ss or left floating. if only one 24wc04 is being addressed on the bus, the address pins (a1 and a2) can be left floating or con- nected to v ss . only two devices can be cascaded when using 24wc08. the only address pin used with this device is a2. the a0 and a1 address pins are no connect pins and can be tied to v ss or left floating. if only one 24wc08 is being addressed on the bus, the address pin (a2) can be left floating or connected to v ss . the 24wc16 is a stand alone device. in this case, all address pins (a0, a1and a2) are no connect pins and can be tied to v ss or left floating. wp: write protect if the wp pin is tied to v cc the entire memory array becomes write protected (read only). when the wp pin is tied to v ss or left floating normal read/write opera- tions are allowed to the device. i 2 c bus protocol the following defines the features of the i 2 c bus proto- col: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat24wc01/02/04/08/16 monitor the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 1010 for the cat24wc01/02/04/08/16 (see fig. 5). the next three significant bits (a2, a1, a0) are the device address bits and define which device or which part of the device the master is accessing. up to eight cat24wc01/ 02, four cat24wc04, two cat24wc08, and one cat24wc16 may be individually addressed by the system. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat24wc01/02/04/08/16 monitors the bus and responds with an acknowledge (on the sda figure 4. acknowledge timing 5020 fhd f06 acknowledge 1 start scl from master 89 data output from transmitter data output from receiver
cat24wc01/02/04/08/16 6 doc. no. 25051-00 3/98 s-1 line) when its address matches the transmitted slave address. the cat24wc01/02/04/08/16 then performs a read or write operation depending on the state of the r/ w bit. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledg- ing device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat24wc01/02/04/08/16 responds with an ac- knowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat24wc01/02/04/08/16 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat24wc01/02/04/08/16 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the cat24wc01/02/04/08/16. after receiving another acknowledge from the slave, the master device transmits the data byte to be written into the addressed memory location. the cat24wc01/02/04/08/16 ac- knowledge once more and the master generates the stop condition, at which time the device begins its internal programming cycle to nonvolatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the cat24wc01/02/04/08/16 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as counter will wrap around to address figure 5. slave address bits 1 0 1 0 a2 a1 a0 r/w 1 0 1 0 a2 a1 a8 r/w 1 0 1 0 a2 a9 a8 r/w 1 0 1 0 a10 a9 a8 r/w 24wc01/02 24wc04 24wc08 24wc16 * a0, a1 and a2 correspond to pin 1, pin 2 and pin 3 of the device. ** a8, a9 and a10 correspond to the address of the memory array address word. *** a0, a1 and a2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
cat24wc01/02/04/08/16 7 doc. no. 25051-00 3/98 s-1 24wcxx f09 figure 7. page write timing 5020 fhd f08 figure 6. byte write timing * p=7 for cat24wc01 and p=15 for cat24wc02/04/08/16 * = don't care for cat24wc01 bus activity: master sda line data n+p byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address note: in this example n = xxxx 0000(b); x = 1 or 0 * the byte write operation, however instead of terminating after the initial word is transmitted, the master is allowed to send up to p (p=7 for 24wc01 and p=15 for cat24wc02/04/08/16) additional bytes. after each byte has been transmitted the cat24wc01/02/04/08/16 will respond with an acknowledge, and internally increment the low order address bits by one. the high order bits remain unchanged. if the master transmits more than p+1 bytes prior to sending the stop condition, the address counter wraps around, and previously transmitted data will be overwrit- ten. once all p+1 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point all received data is written to the cat24wc01/02/04/08/16 in a single write cycle. acknowledge polling the disabling of the inputs can be used to take advan- tage of the typical write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, the cat24wc01/02/04/08/16 initiates the internal write cycle. ack polling can be initiated imme- diately. this involves issuing the start condition followed by the slave address for a write operation. if the cat24wc01/02/04/08/16 is still busy with the write operation, no ack will be returned. if the cat24wc01/ 02/04/08/16 has completed the write operation, an ack will be returned and the host can then proceed with thenext read or write operation. write protection the write protection feature allows the user to protect against inadvertent programming of the memory array. if the wp pin is tied to v cc , the entire memory array is protected and becomes read only. the cat24wc01/ 02/04/08/16 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the devices failure to send an acknowl- edge after the first byte of data is received. read operations the read operation for the cat24wc01/02/04/08/16 is initiated in the same manner as the write operation with the one exception that the r/ w bit is set to a one. three different read operations are possible: immedi- ate address read, selective read and sequential read. immediate address read the cat24wc01/02/04/08/16s address counter con- tains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately follow- ing would access data from address n+1. if n=e (where e = 127 for 24wc01, 255 for 24wc02, 511 for 24wc04, 1023 for 24wc08, and 2047 for 24wc16), then the byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t
cat24wc01/02/04/08/16 8 doc. no. 25051-00 3/98 s-1 0 and continue to clock out data. after the cat24wc01/ 02/04/08/16 receives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the cat24wc01/02/04/08/16 acknowledge the word address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the cat24wc01/02/04/08/16 then re- sponds with its acknowledge and sends the 8-bit byte requested. the master device does not send an ac- knowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the 24wc01/02/04/08/16 sends initial 8-bit byte requested, the master will respond with an acknowledge which tells the device it requires more data. the cat24wc01/02/04/08/16 will continue to output an 8-bit byte for each acknowledge sent by the master. the operation is terminated when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from the cat24wc01/02/ 04/08/16 is outputted sequentially with data from ad- dress n followed by data from address n+1. the read operation address counter increments all of the cat24wc01/02/04/08/16 address bits so that the en- tire memory array can be read during one operation. if more than the e (where e = 127 for 24wc01, 255 for 24wc02, 511 for 24wc04, 1023 for 24wc08, and 2047 for 24wc16) bytes are read out, the counter will wrap around and continue to clock out data bytes. 5020 fhd f10 figure 8. immediate address read timing scl sda 8th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t
cat24wc01/02/04/08/16 9 doc. no. 25051-00 3/98 s-1 24wcxx f14 notes: (1) the device used in the above example is a 24wc02ji-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating voltage, tape & reel) ordering information 5020 fhd f12 figure 10. sequential read timing 24wcxx f11 * = don't care for 24wc01 figure 9. selective read timing ** available for 24wc01 and 24wc02 slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t * bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address prefix device # suffix 24wc02 j i te13 product number 24wc01: 1k 24wc02: 2k 24wc04: 4k 24wc08: 8k 24wc16: 16k tape & reel te13: 2000/reel package p: pdip j: soic (jedec) u: tssop** operating voltage blank: 2.5v - 6.0v 1.8: 1.8v - 6.0v -1.8 cat temperature range blank = commercial (0? - 70?c) i = industrial (-40? - 85?c) a = automotive (-40? - 105?c)* * -40? to +125?c is available upon request optional company id
cat24wc01/02/04/08/16 10 doc. no. 25051-00 3/98 s-1
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